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<p>Structure type to access the Nested Vectored Interrupt Controller (NVIC).  
</p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f">ISER</a> [8]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Interrupt Set Enable Register.  <a href="#af90c80b7c2b48e248780b3781e0df80f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80">RESERVED0</a> [24]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a2de17698945ea49abd58a2d45bdc9c80"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5">ICER</a> [8]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x080 (R/W) Interrupt Clear Enable Register.  <a href="#a1965a2e68b61d2e2009621f6949211a5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">RSERVED1</a> [24]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a6d1daf7ab6f2ba83f57ff67ae6f571fe"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90">ISPR</a> [8]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x100 (R/W) Interrupt Set Pending Register.  <a href="#acf8e38fc2e97316242ddeb7ea959ab90"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72">RESERVED2</a> [24]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a0953af43af8ec7fd5869a1d826ce5b72"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5">ICPR</a> [8]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x180 (R/W) Interrupt Clear Pending Register.  <a href="#a46241be64208436d35c9a4f8552575c5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab">RESERVED3</a> [24]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a9dd330835dbf21471e7b5be8692d77ab"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11">IABR</a> [8]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x200 (R/W) Interrupt Active bit Register.  <a href="#a33e917b381e08dabe4aa5eb2881a7c11"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">RESERVED4</a> [56]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a5c0e5d507ac3c1bd5cdaaf9bbd177790"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c">IP</a> [240]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)  <a href="#a6524789fedb94623822c3e0a47f3d06c"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8">RESERVED5</a> [644]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a4f753b4f824270175af045ac99bc12e8"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__O uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">STIR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xE00 ( /W) Software Trigger Interrupt Register.  <a href="#a0b0d7f3131da89c659a2580249432749"></a><br/></td></tr>
</table>
<hr/><h2>Field Documentation</h2>
<a class="anchor" id="a33e917b381e08dabe4aa5eb2881a7c11"></a><!-- doxytag: member="NVIC_Type::IABR" ref="a33e917b381e08dabe4aa5eb2881a7c11" args="[8]" -->
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<a class="anchor" id="a6524789fedb94623822c3e0a47f3d06c"></a><!-- doxytag: member="NVIC_Type::IP" ref="a6524789fedb94623822c3e0a47f3d06c" args="[240]" -->
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